GDC21D301A Datasheet, PDF (31/35 Pages) Hynix Semiconductor – Transport Decoder

7.4.3 Reset Signal Requirement
\RESET
GDC21D301A
t_RSTw
PARAMETER
PARAMETER
tRSTw
RESET pulse width
MIN
tCLOCKp
TYP
-
The low pulse width of reset signal should be larger than tCLCOKp, the operating clock period.
MAX
-
UNIT
ns
7.4.4 Audio/Video/Data Decoder Interface Requirements
CLOCK
VID_REQ
AUD_REQ
DATA_REQ
VAD_DATA[7:0]
VID_STRB
AUD_STRB
DATA_STRB
t_REQs
t_STRBd t_STRBw
t_VADs
t_VADh
PARAMETER
tVADs
tVADh
tSTRBd
tSTRBw
tREQs
PARAMETER
VAD data setup time
VAD data hold time
STRB to clock delay time
STRB pulse width
REQ setup time
MIN
TYP
MAX UNIT
30
-
-
ns
30
-
-
ns
-
-
18
ns
30
-
-
ns
5
-
-
ns
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