GDC21D301A Datasheet, PDF (13/35 Pages) Hynix Semiconductor – Transport Decoder

5.6 Memory Controller
This controls DRAM interface. It refreshes
DRAM, writes and reads data to and from
DRAM. The corresponding addresses where
the data is written and read are stored in
GDC21D301
DRAM_ADDR[9:0]
DRAM_DATA[15:0]
\D R A M _ R A S 0
\D R A M _ C A S 0
DRAM_RWB
\D R A M _ R A S 1
\D R A M _ C A S 1
M 16
GDC21D301A
pointer memory by the Host processor. The
GDC21D301A requires one or two DRAMs
(256Kx16b or 1Mx16b).
DRAM 0
(256Kx16 or 1Mx16)
A D D R [9:0]
DATA[15:0]
\R A S
\L C A S
\U C A S
RWB
DRAM 1
A D D R [9:0]
DATA[15:0]
\R A S
\L C A S
\U C A S
RWB
Figure 3. External DRAM Interface
5.7 High-Speed Interface
This is an interface block of external high-speed
ports which send whole TS packets.
5.8 External Decoder Interface
This reads data from buffer and sends it to the
corresponding external decoder. It also controls the
input/output of data to and from external decoder.
5.9 Host Interface
Host Processor can access external decoders
through the GDC21D301A transport decoder.
DSP_DATA[15:0] ports are used for data bus.
To access one of the external decoders through the
GDC21D301A,
host
address
bus
(DSP_ADDR[22:0]) should be as follows.
For video decoder access,
DSP_ADDR[22:18] = “100 11”.
For audio decoder access,
DSP_ADDR[22:18] = “100 01”.
For auxiliary decoder access,
DSP_ADDR[21:18] = “100 00”.
5.10 Clock Controller
It outputs two PWM signals(VPWM and APWM)
which can be controlled by the Host Processor. The
PWM signals can be used to control external
VCXOs.
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