GDC21D301A Datasheet, PDF (18/35 Pages) Hynix Semiconductor – Transport Decoder

GDC21D301A
PID Flag 1 (0x00c)
When the GDC21D301A decodes the packet
whose PID is activated for decoding, it sets the
corresponding bit in PID Flag 1, or 2 register.
15
87
0
P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0
FIELD
P15 ~ P3
P2
P1
P0
BITS
15:3
2
1
0
DESCRIPTION
PID flag for PSI_15 ~ PSI_3
Auxiliary PID flag
Audio PID flag
Video PID flag
VALUES
DEFAULT
PID Flag 2(0x00e)
These bits indicate the type of the packet
which the GDC21D301A is now decoding.
15
87
0
P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16
FIELD BITS
DESCRIPTION
P31 ~ P16 15:0 PID flag for PSI_31 ~ PSI_16
VALUES
DEFAULT
APWM control (0x010)
APWM output signal is generated by this value.
External VCXO for audio can be controlled by this
value and the lip synchronization between video
and audio clock. The control of this register is the
same as that of VPWM.
15
87
0
APWM
FIELD
APWM
BITS
DESCRIPTION
15:0 Audio PWM control
VALUES
0x0000 to 0xFFFF
DEFAULT
0x7FFF
19