GDC21D301A Datasheet, PDF (19/35 Pages) Hynix Semiconductor – Transport Decoder

GDC21D301A
VPWM control (0x012)
The chip uses Sigma-delta modulation for VPWM
signal. Modulation clock is 1/34 system
clock(27MHz/34 = 794KHz). VPWM output signal
is generated by this value. When the register value
is 0x7FFF, the period of '1' and the period of '0'
have the same value of 0.630usec, and the cycle
time is 1.259usec, i.e., the duration of VPWM
output signal is 50%. The larger is the value greater
than 0x7FFF, the longer is the high period
generated. For example, if register value is 0x0000,
there is no data of '1' in 65536 data. Only the data
of '0' is almost uniformly distributed in 65536 data.
Adjusting PWM pulse, system VCXO can be
controlled to achieve lip synchronization or system
clocks locking.
15
87
0
VPWM
FIELD
VPWM
BITS
DESCRIPTION
15:0 Video PWM control
VALUES
0x0000 to 0xFFFF
DEFAULT
0x7FFF
Sync Hysteresis (0x014)
15
87
Scd
0
Scl
FIELD
Scd
BITS
DESCRIPTION
7:5 Sync Drop
Scl
4:0 Sync Lock
VALUES
0 = should not be used
1 – 7 = The number of consecutive
sync bytes must be discarded to
constitute a sync drop.
0 = should not be used
1 – 31 = The number of consecutive
sync bytes must be detected
before sync is acquired.
DEFAULT
0x1
0x03
20