GDC21D301A Datasheet, PDF (7/35 Pages) Hynix Semiconductor – Transport Decoder

GDC21D301A
Pin Description (continued)
NAME
PIN
TYPE
DESCRIPTION
HIGH SPEED DATA INTERFACE
\ERR_BLOCK
42
I
FEC Packet Error (active low).
This optional signal may be used to declare that the error has
occurred in a packet. It is used in place of
transport_error_indicator bit in the TS header by the equipment
interfacing with the GDC21D301A.
D_VALID
43
I
FEC Data Valid.
This signal indicates that the data value of FEC_DATA bus is
valid transport stream byte or serial bit. It will be latched in the
internal buffer on the rising edge of FEC_CLOCK.
HSDEN
11
O High Speed Port Data Enable
HIGH_SP_DATA
12, 13
O High Speed Port Data
[1:0]
CLOCK RECOVERY INTERFACE
VPWM
126
O Pulse Width Modulated Pulse1.
Low pass filtered VPWM signal is fed to external VCXO for
adjusting its output frequency.
APWM
101
O Pulse Width Modulated Pulse2.
This is used to lock the Audio clock in the Video clock for lip
synchronization. Low pass filtered APWM signal is fed to the
VCXO.
DRAM INTERFACE
M16
47
I
DRAM 16-Mbit Configuration
DRAM_RWB
49
O DRAM Read/Write.
When you access DRAM, read mode or write mode can be
set as following.
0 : Write mode 1 : Read mode
DRAM_ROW_COL_ 50,51,52,54, O DRAM Parallel Address Bus [9:0].
ADDR[9:0]
55,56,57,59,
Row-column address is multiplexed when you access external
60,61
DRAM. For the fast page mode access, row address is applied
first, and column address is applied next.
DRAM_DATA[15:0] 67,73,74,75, I/O/Z DRAM Parallel Data Bus [15:0].
76,78,79,80,
81,83,84,85,
86,88,89,90
\DRAM_RAS0
64
O DRAM Row Address Strobe0.
Select DRAM0 device. When this signal goes to low, DRAM_
ROW_COL_-ADDR[9:0] has a valid row address.
\DRAM_RAS1
62
O DRAM Row Address Strobe1.
Select the DRAM1 device. When this signal goes to low,
DRAM_ROW_COL_-ADDR[9:0] has a valid row address.
\DRAM_CAS0
66
O DRAM Column Address Strobe0.
Select the low byte DRAM data. When this signal goes to low,
DRAM_-ROW_COL_ADDR[9:0] has a valid column address.
\DRAM_CAS1
65
O DRAM Column Address Strobe1.
Select the high byte DRAM data. When this signal goes to low,
DRAM_-ROW_COL_ADDR[9:0] has a valid column address.
8