GDC21D301A Datasheet, PDF (24/35 Pages) Hynix Semiconductor – Transport Decoder

PID Registers (0x400 ~ 0x47e)
These registers should be written with certain
values during initialization phase, because the
values are undefined at first. Video, audio, and
auxiliary packet will be respectively transferred to
VAD_DATA port with VID_STRB, AUD_STRB,
GDC21D301A
and DATA_STRB signal in case Hig bit in the
register is ‘0’(i.e. High Speed Port has the highest
priority. This is equally applied to other packets.).
Other data will be transferred to the corresponding
buffer in DRAM.
Vid PID Register (0x400, 0x402)
These registers should be written with certain
values during initialization phase, because the
15
8
Den Dst Frm
values are undefined at first. For correct processing,
Dst should be written to ‘0’.
7
0
PID
Field
Den
Dst
Frm
Bits
Description
15 PID enable
14 Decoding state(status reg.)
13 Decoding Type
PID
12:0 PID
Values
1 = PID matching enabled
1 = corresponding PID packet
occurred at least once before
0 = transfer PES_payload to
external port
1 = transfer whole PES packet
Default
These registers should be written with certain
values during initialization phase, because the
values are undefined at first.
15
87
Hig
CCNT
Field
Hig
CCNT
Bits
Description
7
High Speed out enable
3:0 Continuity Counter
Values
1 = transfer whole TS packet to
high speed port
store continuity_counter value
0
Default
Aud PID Register (0x404, 0x406)
Same as Vid PID register, but Audio packet
Aux PID Register (0x408, 0x40a)
Same as Vid PID register, but Auxiliary packet
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