GDC21D301A Datasheet, PDF (6/35 Pages) Hynix Semiconductor – Transport Decoder

GDC21D301A
(Package : 176TQFP)
NAME
CLOCK
CLOCK_27M
CLOCK_OUT
\RESET
TEST
TA[9:0]
TDI
TWEB
TDO0
TDO1
P_S_MODE
FEC_DATA[7:0]
F_START
FEC_CLOCK
PIN
TYPE
DESCRIPTION
CLOCKS & RESET
157
I
Operation clock.
The frequency of operating clock is 27MHz and it should be
locked in encoder system clock. The clock may be supplied by
external VCXO controlled by VPWM.
69
I
27MHz clock.
It is used to count STC value. This clock may be supplied by
external VCXO controlled by VPWM.
14
O Operation Clock Output.
For high-speed output data
112
I
Global Reset (active low)
The signal asynchronously resets the GDC21D301A.
TEST INTERFACE (for IC self-test purpose only)
26
I
Test Mode
46,44,16,17,
I
Test address.
18,19,20,21,2
TA[9] and TA[8] are respectively multiplexed with SCAN_IN1
2,23
and SCAN_MODE pins.
27
I
Test Input Data
25
I
Test Write Enable (active low)
8
O Test Output Data0
9
O Test Output Data1
TRANSPORT STREAM INTERFACE
28
I
FEC Data Input Mode Selection.
0: byte-parallel input mode
1: bit-serial input mode
30,31,36,37,
I
TS Data.
38,39,40,41
It is used for byte-parallel or bit-serial transfers of a coded TS
data to the device. In bit-serial mode, FEC_DATA[0] is a serial
data input for TS data.
29
I
FEC Sync Byte Indicator.
F_START is valid in bit-serial input mode only. FEC_DATA
is aligned by the byte parallel with this signal. This signal
should be activated at the first bit of the TS sync byte or every
first bit of the data byte.
32
I
FEC Data Clock.
FEC_CLOCK is used to latch a data byte or a single bit of
coded TS into the device on the rising edge. FEC_CLOCK may
be asynchronous with the device. The value of FEC_DATA is
locked into the GDC21D301A internal buffer on the rising
edge of FEC_CLOCK, if D_VALID is asserted HIGH.
7