GMS81004 Datasheet, PDF (72/101 Pages) Hynix Semiconductor – 8-BIT SINGLE CHIP MICROCOMPUTERS

Chapter 5. Interrupt
Clock
SYNC
R/W
INTERNAL
ADDR. BUS
INTERNAL
DATA BUS
INTERNAL
READ
Interrupt Process Step
PC
SP
SP-1
SP-2
OP
OP
CODE CODE
PCH
PCL
PSW
ISR^*1
LVA*2 HVA*3
NEW PC
¡ÈL¡È
¡ÈH¡È
VECTOR VECTOR
INTERNAL
WRITE
Fig. 5. 3 Interrupt Procesing Step Timing
*1 ISR : Interrupt Service Routine
*2 LVA : Low Vector Address
*3 HVA : High Vector Address
5.1 SOFTWARE INTERRUPT
5.5.1 Interrupt by Break(BRK) Instruction
Software interrupt is available just by writing ¡ÈBreak(BRK)¡È instruction.
The values of PC and PSW is stacked by BRK instruction and then B flag of PSW is set
and I flag is reset.
Flag change by BRK execution
N
V
G
B
H
I
Z
C
PSW
set
reset
N
V
G
1
H
0
Z
C
PSW
(Right after BRK execution)
5 -7