GMS81004 Datasheet, PDF (70/101 Pages) Hynix Semiconductor – 8-BIT SINGLE CHIP MICROCOMPUTERS

5.3.2 Interrupt Timing
Chapter 5. Interrupt
CLOCK
SYNC
A command before interrupt
interrupt process step
Interrupt Request Sampling
Fig. 5.2 Interrupt Enable Accept Timing
Interrupt Request
sampling time
Maximum 12 machine cycle (When execute DIV instruction)
Minimum 0 machine cycle
Interrupt preprocess step is 8 machine cycle
Interrupt overhead
Maximum 1 + 12 + 8 = 21 machine cycle
Minimum 1 + 0 + 8 = 9 machine cycle
5.3.3 The valid timing after executing Interrupt control instructions
I flag is valid just after executing of EI/DI on the contrary.
Interrupt Enable register is valid one instruction after controlling interrupt Enable
Register.
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