GMS81004 Datasheet, PDF (69/101 Pages) Hynix Semiconductor – 8-BIT SINGLE CHIP MICROCOMPUTERS

Chapter 5. Interrupt
5.3 INTERRUPT ACCEPT MODE
The interrupt priority order is determined by bit(IM1, IM0) of IMOD register.
IMOD
7
-
-
IM1
0
0
1
Interrupt Mode Register
0
IM1
IM0
IP3
IP2
IP1
IP0
Assigning by interrupt accept mode bit
IM0
Priority
0
Fixed by H/W
1
Changeable by IP 3-0
*
Interrupt is inhibited
R/W <00CAH>
5.3.1 Selection of interrupt by IP3 - IP0
The condition allow for accepting interrupt is set state of the interrupt mask enable flag
and the interrupt enable bit must be ¡È1¡È.
IP3
IP2
IP1
IP0
Selection interrupt
0
0
0
1
KSCNR (Key Scan)
0
0
1
0
INT1R (External interrupt 1)
0
0
1
1
INT2R (External interrupt 2)
0
1
0
0
Reserved
0
1
0
1
T0R (Timer 0)
0
1
1
0
T1R (Timer 1)
0
1
1
1
T2R (Timer 2)
1
0
0
0
Reserved
1
0
0
1
Reserved
1
0
1
0
WDTR (Watch Dog Timer)
1
0
1
1
BITR (Basic Interval Timer)
1
1
0
0
Reserved
Table 5.2 Interrupt Selection by IP3 - IP0
*In Reset state, these IP3 - IP0 registers become all ¡È0¡È.
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