GMS81004 Datasheet, PDF (68/101 Pages) Hynix Semiconductor – 8-BIT SINGLE CHIP MICROCOMPUTERS

Chapter 5. Interrupt
5.2 INTERRUPT CONTROL REGISTER
I flag of PSW is a interrupt mask enable flag. When I flag = ¡È0¡È, all interrupts become
disable. When I flag = ¡È1¡È, interrupts can be selectively enabled and disabled by
contents of corresponding Interrupt Enable Register.
When interrupt is occured, interrupt request flag is set, and Interrupt request is detected
at the edge of interrupt signal. The accepted interrupt request flag is automatically
cleared during interrupt cycle process. The interrupt request flag maintains ¡È1¡È until
the interrupt is accepted or is cleared in program.
In reset state, interrupt request flag register(IRQH, IRQL) is cleared to ¡È0¡È. It is
possible to read the state of interrupt register and to mainpulate the contents of register
and to generate interrupt. (Refer to software interrupt).
Interrupt Enable Register Low
7
IENL
-
WDTR BITE
-
-
-
-
0
-
R/W <00CCH>
IENH
Interrupt Enable Register High
7
KSCNE INT1E INT2E
-
T0E
T1E
T2E
0
-
R/W <00CEH>
Interrupt Request Register Low
7
IRQL
-
WDTR BITE
-
-
-
-
0
-
R/W <00CDH>
IRQH
7
KSCNR
INT1R
Interrupt Request Register High
INT2R
-
T0R
T1R
T2R
0
-
R/W <00CFH>
5 -3