HY5S5B6GLF-6 Datasheet, PDF (7/52 Pages) Hynix Semiconductor – 256Mbit (16Mx16bit) Mobile SDR Memory

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256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
BALL DESCRIPTION
SYMBOL
CLK
CKE
CS
BA0, BA1
A0 ~ A12
RAS, CAS, WE
UDQM, LDQM
DQ0 ~ DQ15
VDD/VSS
VDDQ/VSSQ
NC
TYPE
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
I/O
SUPPLY
SUPPLY
-
DESCRIPTION
Clock : The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
Clock Enable : Controls internal clock signal and when deactivated, the SDRAM will
be one of the states among (deep) power down, suspend or self refresh
Chip Select : Enables or disables all inputs except CLK, CKE, UDQM and LDQM
Bank Address : Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address : RA0 ~ RA12, Column Address : CA0 ~ CA8
Auto-precharge flag : A10
Command Inputs : RAS, CAS and WE define the operation
Refer function truth table for details
Data Mask : Controls output buffers in read mode and masks input data in write
mode
Data Input/Output : Multiplexed data input/output pin
Power supply for internal circuits
Power supply for output buffers
No connection
Rev 1.0 / Apr. 2006
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