HY5S5B6GLF-6 Datasheet, PDF (12/52 Pages) Hynix Semiconductor – 256Mbit (16Mx16bit) Mobile SDR Memory

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256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
Parameter
System Clock Cycle Time CAS Latency=3
Clock High Pulse Width
Clock Low Pulse Width
Access Time From Clock CAS Latency=3
Data-out Hold Time
Data-Input Setup Time
Data-Input Hold Time
Address Setup Time
Address Hold Time
CKE Setup Time
CKE Hold Time
Command Setup Time
Command Hold Time
CLK to Data Output in Low-Z Time
CLK to Data Output in
High-Z Time
CAS Latency=3
6
H
S
Symbol
Unit Note
Min Max Min Max Min Max
tCK3
6.0 1000 7.5 1000 9.5 1000 ns
tCHW
2.0 -
2.5 -
3.0
-
ns
1
tCLW
2.0 -
2.5 -
3.0
-
ns
1
tAC3
- 5.4 - 6.5 - 7.0 ns 2
tOH
2.0 -
2.0 -
2.0
-
ns
tDS
2.0 -
2.0 -
2.0
-
ns
1
tDH
1.0 -
1.0 -
1.0
-
ns
1
tAS
2.0 -
2.0 -
2.0
-
ns
1
tAH
1.0 -
1.0 -
1.0
-
ns
1
tCKS
2.0 -
2.0 -
2.0
-
ns
1
tCKH
1.0 -
1.0 -
1.0
-
ns
1
tCS
2.0 -
2.0 -
2.0
-
ns
1
tCH
1.0 -
1.0 -
1.0
-
ns
1
tOLZ
1.0 -
1.0 -
1.0
-
ns
tOHZ3
5.4
6.5
7.0 ns
Note :
1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter.
2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR > 1ns,
then (tR/2-0.5)ns should be added to the parameter.
Rev 1.0 / Apr. 2006
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