HY5S5B6GLF-6 Datasheet, PDF (4/52 Pages) Hynix Semiconductor – 256Mbit (16Mx16bit) Mobile SDR Memory

11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
FEATURES
● Standard SDRAM Protocol
● Clock Synchronization Operation
- All the commands registered on positive edge of basic input clock (CLK)
● MULTIBANK OPERATION - Internal 4bank operation
- During burst Read or Write operation, burst Read or Write for a different bank is performed.
- During burst Read or Write operation, a different bank is activated and burst Read or Write
for that bank is performed
- During auto precharge burst Read or Write, burst Read or Write for a different bank is performed
● Power Supply Voltage : VDD = 1.8V, VDDQ = 1.8V
● LVCMOS compatible I/O Interface
● Low Voltage interface to reduce I/O power
● Programmable burst length: 1, 2, 4, 8 or full page
● Programmable Burst Type : sequential or interleaved
● Programmable CAS latency of 3
● Programmable Drive Strength
● Low Power Features
- Programmable PASR(Partial Array Self Refresh)
- Auto TCSR (Temperature Compensated Self Refresh)
- Programmable DS (Drive Strength)
- Deep Power Down Mode
● -25^oC ~ 85^oC Operation Temperature
- Extended Temp. : -25^oC ~ 85^oC
● Package Type : 54ball, 0.8mm pitch FBGA (Lead Free, Lead), 8 x 10 [mm²], t=0.1mm max
HY5S5B6GLFP : Lead Free
HY5S5B6GLF : Leaded
Rev 1.0 / Apr. 2006
4