HY5S5B6GLF-6 Datasheet, PDF (2/52 Pages) Hynix Semiconductor – 256Mbit (16Mx16bit) Mobile SDR Memory

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256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
Document Title
4Bank x 4M x 16bits Synchronous DRAM
Revision History
Revision No.
0.1
0.2
1.0
History
Initial Draft
1. Changed
166MHz IDD1 : 60mA --> 75mA
133MHz IDD1 : 55mA --> 65mA
105MHz IDD1 : 50mA --> 55mA
2. Remove
CL2 operation (Page 13 to 14)
1. Release
Draft Date
Feb. 2006
Mar. 2006
Apr. 2006
Remark
Preliminary
Preliminary
Final
Rev 1.0 / Apr. 2006
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