HY5PS1G431CFP_08 Datasheet, PDF (34/45 Pages) Hynix Semiconductor – 1Gb DDR2 SDRAM

HY5PS1G4(8,16)31C(L)FP
HY5PS1G4(8,16)31CFR
Fig. d. Illustration of tangent line for tIH, tDH
CK, DQS
CK, DQS
V_DDQ
V_IH(ac)min
V_IH(dc)min
t_IS, t_IH,
t_DS
t_DH
V_REF(dc)
V_IL(dc)max
dc to V_REF
region
Tangent
line
t_IS, t_IH,
t_DS t_DH
tangent
line
nominal
line
nominal
line
V_IL(ac)max
Vss
Delta TR
Delta TF
Hold Slew Rate
Rising Signal
=
Tangent line[VREF(dc)-V_IL(ac)max]
Delta TR
Hold Slew Rate
Falling Signal
= ^{Tangent line[VIH(ac)min-VREF(dc)]}
Delta TF
Rev. 0.7 / Nov. 2008
34