HY5PS1G431CFP_08 Datasheet, PDF (29/45 Pages) Hynix Semiconductor – 1Gb DDR2 SDRAM

HY5PS1G4(8,16)31C(L)FP
HY5PS1G4(8,16)31CFR
Specific Notes for dedicated AC parameters
1. User can choose which active power down exit timing to use via MRS(bit 12). tXARD is expected to be
used for fast active power down exit timing. tXARDS is expected to be used for slow active power down exit
timing where a lower power value is defined by each vendor data sheet.
2. AL = Additive Latency
3. This is a minimum requirement. Minimum read to precharge timing is AL + BL/2 providing the tRTP and
tRAS(min) have been satisfied.
4. A minimum of two clocks (2 * tCK or 2 * nCK) is required irrespective of operating frequency
5. Timings are specified with command/address input slew rate of 1.0 V/ns. See System Derating for other
slew rate values.
6. Timings are guaranteed with DQs, DM, and DQS’s (DQS/RDQS in singled ended mode) input slew rate of
1.0 V/ns. See System Derating for other slew rate values.
7. Timings are specified with CK/CK differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS signals
with a differential slew rate of 2.0 V/ns in differential strobe mode and a slew rate of 1V/ns in single ended
mode. See System Derating for other slew rate values.
8. tDS and tDH derating
DQ
Slew
rate
V/ns
DQ
Slew
rate
V/ns
tDS, tDH Derating Values for DDR2-400, DDR2-533(ALL units in 'ps', Note 1 applies to entire Table)





DQS, DQS Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns
¦¦¦¦¦¦¦¦¦¦¦¦¦¦¦¦¦¦
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
2.0 125 45 125 45 +125 +45 - - - - - - - - - - - -
1.5 83 21 83 21 +83 +21 95 33 - - - - - - - - - -
1.0 0 0 0 0 0 0 12 12 24 24 - - - - - - - -
0.9 - - -11 -14 -11 -14 1 -2 13 10 25 22 - - - - - -
0.8 - - - - -25 -31 -13 -19 -1 -7 11 5 23 17 - - - -
0.7 - - - - - - -31 -42 -42 -19 -7 -8 5 -6 17 6 - -
0.6 - - - - - - - - -43 -59 -31 -47 -19 -35 -7 -23 5 -11
0.5 - - - - - - - - - - -74 -89 -62 -77 -50 -65 -38 -53
0.4 _tDS-_{, tDH D}- _eratin-_{g Valu}-_{es for}-_DDR2-_{-667, D}-_DR2-8-_00(AL-_{L units}- _{in 'ps}-_{', Note}- _{1 ap}-1_p2_li7_es -_t1_o4_e0_nti-_r1_e1_T5_ab-_l1_e2₎ 8 -103 -116





DQS, DQS Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns
¦¦¦¦¦¦¦¦¦¦¦¦¦¦¦¦¦¦
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
2.0 100 45 100 45 100 45 -
-
-
-
-
-
-
-
-
-
-
-
1.5 67 21 67 21 67 21 79 33 -
-
-
-
-
-
-
-
-
-
1.0 0 0 0 0 0 0 12 12 24 24 -
-
-
-
-
-
-
-
0.9 -
- -5 -14 -5 -14 7 -2 19 10 31 22 -
-
-
-
-
-
0.8 -
-
-
- -13 -31 -1 -19 11 -7 23 5 35 17 -
-
-
-
0.7 -
-
-
-
-
- -10 -42 2 -30 14 -18 26 -6 38 6
-
-
0.6 -
-
-
-
-
-
-
- -10 -59 2 -47 14 -35 26 -23 38 -11
0.5 -
-
-
-
-
-
-
-
-
- -24 -89 -12 -77 0 -65 12 -53
0.4 -
-
-
-
-
-
-
-
-
-
-
- -52 -140 -40 -128 -28 -116
1) For all input signals the total tDS(setup time) and tDH(hold time) required is calculated by adding the datasheet value to the derating
Rev. 0.7 / Nov. 2008
29