HY5PS1G431CFP_08 Datasheet, PDF (18/45 Pages) Hynix Semiconductor – 1Gb DDR2 SDRAM

HY5PS1G4(8,16)31C(L)FP
HY5PS1G4(8,16)31CFR
IDD Test Conditions
(IDD values are for full operating range of Voltage and Temperature, Notes 1-5)
Symbol
Conditions
Units
IDD0
Operating one bank active-precharge current; ^tCK = ^{tCK(IDD), tRC} = ^{tRC(IDD), tRAS} = ^tRAS
min(IDD); CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are SWITCH-
mA
ING;Data bus inputs are SWITCHING
IDD1
Operating one bank active-read-precharge DVSSFOU; IOUT = 0mA;BL = 4, CL = CL(IDD), AL
= 0; ^tCK = ^{tCK(IDD), tRC} = ^tRC (IDD), ^tRAS = ^{tRASmin(IDD), tRCD} = ^tRCD(IDD); CKE is HIGH, CS
is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as
mA
IDD4W
IDD2P ^{Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and} mA
address bus inputs are STABLE; Data bus inputs are FLOATING
IDD2Q ^{Precharge quiet standby current;All banks idle; tCK = tCK(IDD);CKE is HIGH, CS is HIGH;}
mA
Other control and address bus inputs are STABLE; Data bus inputs are FLOATING
IDD2N ^{Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other}
mA
control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Active power-down current; All banks open; ^tCK = ^tCK(IDD); _{Fast PDN Exit MR(12) = 0}
mA
IDD3P CKE is LOW; Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
Slow PDN Exit MR(12) = 1
mA
Active standby current; All banks open; ^tCK = ^{tCK(IDD), tRAS} = ^{tRASmax(IDD), tRP}
IDD3N _{=tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Other control and address bus}
mA
inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD),
IDD4W AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between mA
valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL
IDD4R ^{= CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is}
mA
HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as
IDD4W
Burst refresh current; ^tCK = ^tCK(IDD); Refresh command at every ^tRFC(IDD) interval; CKE is
IDD5B HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCH-
mA
ING; Data bus inputs are SWITCHING
IDD6
Self refresh current; CK and CK at 0V; CKE ≤ 0.2V; Other control and address bus inputs are
FLOATING; Data bus inputs are FLOATING
mA
IDD7
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL
= CL(IDD), AL = ^{tRCD(IDD)-1*tCK(IDD); tCK} = ^{tCK(IDD), tRC} = ^{tRC(IDD), tRRD} = ^tRRD(IDD),
tRCD _{= 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are}
mA
STABLE during DESELECTs; Data pattern is same as IDD4R; - Refer to the following page for
detailed timing conditions
Rev. 0.7 / Nov. 2008
18