HY5PS1G431CFP_08 Datasheet, PDF (26/45 Pages) Hynix Semiconductor – 1Gb DDR2 SDRAM

Parameter
Internal write to read command delay
Internal read to precharge command delay
Exit self refresh to a non-read command
Exit self refresh to a read command
Exit precharge power down to any non-read
command
Exit active power down to read command
Exit active power down to read command
(Slow exit, Lower power)
CKE minimum pulse width
(HIGH and LOW pulse width)
ODT turn-on delay
ODT turn-on
ODT turn-on(Power-Down mode)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down mode)
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
Minimum time clocks remains ON after CKE
asynchronously drops LOW
HY5PS1G4(8,16)31C(L)FP
HY5PS1G4(8,16)31CFR
-Continued-
Symbol
tWTR
tRTP
tXSNR
tXSRD
tXP
tXARD
tXARDS
DDR2-667
min
max
7.5
-
7.5
tRFC + 10
200
-
2
-
2
7 - AL
DDR2-800
min
max
7.5
-
7.5
tRFC + 10
200
-
2
-
2
8 - AL
Unit Notes
ns
24,32
ns
3,32
ns
32
nCK
nCK
nCK
1
nCK
1, 2
tCKE
tAOND
tAON
tAONPD
tAOFD
tAOF
tAOFPD
tANPD
tAXPD
tOIT
tDelay
3
3
2
tAC(min)
tAC(min)+2
2.5
2
tAC(max)
+0.7
2tCK(avg)+
tAC(max)+1
2.5
2
tAC(min)
tAC(min)
+2
2.5
tAC(min) tAC(max)+ 0.6 tAC(min)
tAC(min)
+2
3
8
0
2.5tCK(avg)+
tAC(max)+1
12
tIS + tCK (avg)
+ tIH
tAC(min)
+2
3
8
0
tIS + tCK
(avg)
+ tIH
2
tAC(max)
+0.7
2tCK(avg)+
tAC(max)+1
2.5
tAC(max)
+0.6
2.5tCK(avg)+
tAC(max)+1
12
nCK
27
nCK
16
ns 6,16,40
ns
nCK 17,45
ns
17,43,4
5
ns
nCK
nCK
ns
32
ns
15
Rev. 0.7 / Nov. 2008
26