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| HY5PS1G431CFP_08 Datasheet, PDF (33/45 Pages) Hynix Semiconductor – 1Gb DDR2 SDRAM | |||
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Fig. c. Illustration of nominal line for tIH, tDH
HY5PS1G4(8,16)31C(L)FP
HY5PS1G4(8,16)31CFR
CK, DQS
CK, DQS
VDDQ
VIH(ac)min
tIS,
tIH,
tDS
tDH
VIH(dc)min
dc to VREF
region
VREF(dc)
VIL(dc)max
nominal
slew rate
tIS,
tIH,
tDS
tDH
nominal
slew rate
VIL(ac)max
Vss
Delta TR
Delta TF
Hold Slew Rate
Rising Signal
=
VREF(dc)-VIL(dc)max
Delta TR
Hold Slew Rate
Falling Signal
=
VIH(dc)min - VREF(dc)
Delta TF
Rev. 0.7 / Nov. 2008
33
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