HMC701LP6CE Datasheet, PDF (37/46 Pages) Hittite Microwave Corporation – 8 GHz 16-Bit Fractional-N Synthesizer

v03.0709
HMC701LP6CE
8 GHz 16-Bit Fractional-N Synthesizer
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Table 12. Reg 01h Enable & Reset Register
Bit
Type
Name
Default
0
R/W malg_vcobug_en
1
1
1
R/W mag_bias_en
1
1
2
R/W rfp_div_en
1
0
3
R/W xrefmux_todig_en
4
R/W rfp_div_todig_en
5
R/W rfp_sqr_todig_en
6
R/W rfp_sin_todig_en
7
R/W rfp_bug_sq_en
8
R/W rfp_bug_sin_en
9
R/W vcop_todig_en
10
R/W vcop_presc_en
11
R/W pfd_lkd_en
12
R/W cp_en
13
R/W dsm_rstb
14
R/W lkd_rstb
15
R/W pfds_rstb
1
1
1
0
1
0
1
0
1
1
1
0
1
0
1
1
1
0
1
1
1
0
1
0
1
1
Description
VCO Buffer Enable
Bias enable
Enables / Holds refdiv in reset
Holding Ref divider in reset is equivalent to
bypassing the divider, see Figure 10
Enables clock gate for xtal muxed (sq or sin)
reference to digital
Enables divided reference clock to the digital
see Figure 10
Enables square wave xtal clock to main digital
see Figure 10
Enables sine wave xtal clock to main digital
see Figure 10
Enables Square wave Ref Buffer, see Figure 10
Enables Sine wave Ref Buffer, see Figure 10
1= divided VCO as digital, Δ∑ modulator clock
0= Divided Ref path as the
Enables the prescaler bias
Enable / Resetb to digital lockdetect circuit and
PFD’s lockdetect output gates
Charge Pump Enable, disable is tri-stated output
1 - Enables fractional modulator
see also dsm_integer_mode Reg12h<3>
1 - enables lock detect circuit
CSP PFD FF rstb
1 - Enables the Cycle Slip Prevention (CSP)
feature of the PFD
Table 13. Reg 02h Serial Data Out Force Register
Bit
Type
Name
Default
0
R/W malg_sdo_driver_force_val
1
1
R/W malg_sdo_driver_force_en
1
Description
Serial Data Out Force value
This value may be forced onto LD_SDO by
setting malg_sdo_driver_force_en
Serial Data Out EN Force enable
Places value from malg_sdo_driver_force_val on
SDO
11 - 38
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