HMC701LP6CE Datasheet, PDF (23/46 Pages) Hittite Microwave Corporation – 8 GHz 16-Bit Fractional-N Synthesizer

v03.0709
HMC701LP6CE
8 GHz 16-Bit Fractional-N Synthesizer
11
A normal 3 sigma peak-to-peak variation in the arrival time therefore would be
If the synthesizer was in fractional mode, the fractional modulation of the VCO divider will dominate the jitter. The exact
standard deviation of the divided VCO signal will vary based upon the modulator chosen, however a typical modulator
will vary by about ±3 VCO periods, ±4 VCO periods, worst case.
If, for example, a nominal VCO at 5 GHz is divided by 100 to equal the reference at 50 MHz, then the worst case
division ratios will vary by 100±4. Hence the peak variation in the arrival times caused by Δ∑ modulation of the
fractional synthesizer at the reference will be
(EQ 11)
In this example, T_{jΔ∑pk} = ±200 ps(104-96)/2 = ±800 psec. If we note that the distribution of the delta sigma modulation
is approximately gaussian, we could approximate T_{jΔ∑pk} as a 3 sigma jitter, and hence we could estimate the rms jitter
of the Δ∑ modulator as about 1/3 of T_{jΔ∑pk} or about 266 psec in this example.
Hence the total rms jitter T_j, expected from the delta sigma modulation plus the phase noise of the VCO would be given
by the rms sum , where
(EQ 12)
In this example the jitter contribution of the phase noise calculated previously would add only 0.764psec more jitter at
the reference, hence we see that the jitter at the phase detector is dominated by the fractional modulation.
Bottom line, we have to expect about ±0.8 nsec of normal variation in the phase detector arrival times when in
fractional mode. In addition, lower VCO frequencies with high reference frequencies will have much larger variations.,
for example, a 1 GHz VCO operating at near the minimum nominal divider ratio of 36, would, according to (EQ 11),
exhibit about ±4 nsec of peak variation at the phase detector, under normal operation. The lock detect circuit must not
confuse this modulation as being out of lock.
PFD Lock Detect
lkd_en (Reg01h<11> Table 12) enables the lock detect functions of the HMC701LP6CE.
The Lock Detect circuit in the HMC701LP6CE places a one shot window around the reference. The one shot window
may be generated by either an analog one shot circuit or a digital one shot based upon an internal ring oscillator timer.
Clearing lkd_ringosc_mono_select (Reg1Ah<14> Table 36) will result in a nominal ±10nsec ‘analog’ window of fixed
length, as shown in Figure 21. Setting lkd_ringosc_mono_select will result in a variable length ’digital’ widow. The
digital one shot window is controlled by lkd_ringosc_cfg (Reg1Ah<16:15>). The resulting lock detect window period is
then generated by the number of ring oscillator periods defined in lkd_monost_duration Reg1Ah<18:17> (Table 36).
The lock detect ring oscillator may be observed on the GPO2 port by setting ringosc_testmode (Reg1Ah<19> Table
36) and configuring the gpo_sel<3:0> = 0111 in (Reg1Bh Table 37). Lock detect does not function when this test mode
is enabled.
lkd_wincnt_max (Reg1Ah<9:0> Table 36) defines the number of consecutive counts of the VCO that must land inside
the lock detect window to declare lock. If for example we set lkd_wincnt_max = 1000 , then the VCO arrival would
have to occur inside the selected lock widow 1000 times in a row to be declared locked. When locked the Lock Detect
flag ro_lock_detect (Reg1Fh<0> Table 41) will be set. A single occurrence outside of the window will result in clearing
the Lock Detect flag, ro_lock_detect.
11 - 24
For price, delivery, and to place orders, please contact Hittite Microwave Corporation:
20 Alpha Road, Chelmsford, MA 01824 Phone: [phone] Fax: [phone]
Order On-line at www.hittite.com