HMC701LP6CE Datasheet, PDF (34/46 Pages) Hittite Microwave Corporation – 8 GHz 16-Bit Fractional-N Synthesizer

v03.0709
HMC701LP6CE
8 GHz 16-Bit Fractional-N Synthesizer
The msbs of Reg0Bh, are VCO control bits and are also VCO specific. The VCO should be designed to only register
the data upon receipt of the latch signal, VSLE.
Multiple VCO control can be implemented by addressing the individual VCOs.
VCO Serial Port WRITE Operation
DVDD = 3V ±10%, DGND = 0V
Table 5. Timing Characteristics
Parameter
Conditions
t₁
VSLE to VSDO setup time
t₂
VSDO to VSCK setup time
t₃
VSDO to VSCK hold time
t₄
VSCK high duration
t₅
VSCK low duration
t₆
VSLE high duration
Min.
8
10
10
8
8
8
Typ.
Max
Units
nsec
nsec
nsec
nsec
nsec
nsec
VCO Serial port status is flagged in Read Only register spi_vco_busy (Reg1Fh<4> Table 41).
Individual step tuned VCOs may have different capabilities, such as power down, or divide by two outputs, and may
also have different number of switches in the resonator. The HMC701LP6CE can adapt its control format and number
of tuning bits used in the autotuning routine as described in Reg0Dh Table 24.
16-Bit VCO Write Cycle
HMC VCOs that support the 16-bit write cycle described here are fully addressable via the VSPI control.
A typical 16-bit VCO WRITE cycle is shown in Figure 31.
a. The Synthesizer (Master) both clears VSLE (VCO Serial Port Latch) and places data bit d8 (msb) on VSDO.
b. the synthesizer places a rising edge on VSCK to shift d8 into the VCO
c. Synthesizer places the next eight data bits, d7:d0, on the next eight falling edges of VSCLK, LSB last.
d. The synthesizer clocks each data bit on the next eight rising edges of VSCLK .
e. Synthesizer places the next four VCO Register bits, r3:r0, on the next four falling edges of VSCLK, LSB last.
f. Synthesizer places the next three VCO address bits, a2:a0, on the next three falling edges of
VSCLK, LSB last.
g. The synthesizer asserts VSLE after the falling edge of the 16th VSCK, which latches the data into the VCO
h. the synthesizer clears VSLE to complete the cycle
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Figure 31. VCO Serial Port Timing Diagram - WRITE ONLY
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