HMC701LP6CE Datasheet, PDF (22/46 Pages) Hittite Microwave Corporation – 8 GHz 16-Bit Fractional-N Synthesizer

v03.0709
HMC701LP6CE
8 GHz 16-Bit Fractional-N Synthesizer
PFD Jitter & Lock Detect Background
In normal phase locked operation the divided VCO signal arrives at the phase detector in phase with the divided
crystal signal, known as the reference signal. Despite the fact that the device is in lock, the phase of the VCO signal
and the reference signal vary in time due to the phase noise of the crystal and VCO oscillators, the loop bandwidth
used and the presence of fractional modulation or not. The total integrated noise on the VCO path normally dominates
the variations in the two arrival times at the phase detector if fractional modulation is turned off.
If we wish to detect if the VCO is in lock or not we need to distinguish between normal phase jitter when in lock and
phase jitter when not in lock.
First, we need to understand what is the jitter of the synthesizer, measured at the phase detector in integer or fractional
modes.
The standard deviation of the arrival time of the VCO signal, or the jitter, in integer mode may be estimated with a
simple approximation if we assume that the locked VCO has a constant phase noise, Ф² (ƒ₀), at offsets less than
the loop 3 dB bandwidth and a 20 dB per decade roll off at greater offsets. The simple locked VCO phase noise
approximation is shown on the left of Figure 20.
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Figure 20. Synthesizer Phase Noise & Jitter
With this simplification the single sideband integrated VCO phase noise, Ф² , in rads² at the phase detector is given
by
(EQ 9)
where
Ф² _SSB(ƒ₀) is the single sideband phase noise in rads²/Hz inside the loop bandwidth, B is the 3 dB corner frequency of
the closed loop PLL and N is the division ratio of the prescaler
The rms phase jitter of the VCO in rads, Ф , results from the power sum of the two sidebands:
Ф = √ 2Ф2
SSB
(EQ 10)
Since
the
simple
integral
of
(EQ
9)
is
just
a
product
of
constants,
we
can
±3
easily
√_do2T_thjpen
= 0.756
integral
ps
in
the
log
domain.
For example if the VCO phase noise inside the loop is -100 dBc/Hz at 10 kHz offset and the loop bandwidth is
100 kHz, and the division ratio N=100, then the integrated single sideband phase noise at the phase detector in dB is
given by Ф²_dB = 10log (Ф²(ƒ₀)Bπ ⁄ N²) = -100 + 50 + 5 - 40 = -85 dBrads, or equivalently Ф = 10^-82/20 = 56 urads rms or
3.2 milli-degrees rms.
While the phase noise reduces by a factor of 20logN after division to the reference, the jitter is a constant.
The rms jitter from the phase noise is then given by T_jnp = T_ref Ф / 2π
In this example if the reference was 50 MHz, T_ref = 20 nsec, and hence T_jpn = 178 femto-sec.
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