HMC701LP6CE Datasheet, PDF (25/46 Pages) Hittite Microwave Corporation – 8 GHz 16-Bit Fractional-N Synthesizer

v03.0709
HMC701LP6CE
8 GHz 16-Bit Fractional-N Synthesizer
The HMC701LP6CE PFD features Cycle Slip Prevention (CSP), an ability to virtually eliminate cycle slipping during
acquisition. When enabled, the CSP feature essentially holds the PFD gain at maximum until such time as the
frequency difference is near zero. CSP allows significantly faster lock times as shown in Figure 23. The use of the
CSP feature is enabled with pfds_rstb (Reg01<15> Table 12). The CSP feature may be optimized for a given set
of PLL dynamics by adjusting the PFD sensitivity to cycle slipping. This is achieved by adjusting pfds_sat_deltaN
(Reg1C<3:0> Table 38).
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Figure 23. Cycle Slip Prevention (CSP)
Charge Pump Gain
A simplified diagram of the charge pump is shown in Figure 24. Charge pump up and down gains are set by cp_
UPcurrent_sel and cp_DNcurrent_sel respectively (Reg07 Table 18). Normally the registers are set to the same
value. Each of the UP and DN charge pumps consist of 5-bit charge pumps with lsb of 125 µA. The current gain of the
pump, in Amps/radian, is equal to the gain setting of this register divided by 2π.
For example if both cp_UPcurrent_sel and cp_DNcurrent_sel are set to ’01000’ the output current of each pump will
be 1mA and the gain Kp = 1mA/2π radians, or 159 uA/rad.
Charge Pump Gain Trim
In most applications Gain Trim is not used. However it is available for special applications.
Each of the UP and DN pumps may be trimmed separately to more precise values to improve current source matching
of the UP and DN values, or to allow finer control of pump gain.
The pump trim controls are 3-bits, binary weighted for UP and DN, in cp_UPtrim_sel and cp_DNtrim_sel respectively
(Reg 08h Table 19). LSB weight is 14.7 uA, x000 = 0 trim, x001 = 14.7 ua added trim, x111 = 100uA.
Charge Pump Phase Offset
Either of the UP or DN charge pumps may have a DC leakage or “offset” added. The leakage forces the phase detector
to operate with a phase offset between the reference and the divided VCO inputs. It is recommended to operate with
a phase offset when using fractional mode to reduce non-linear effects from the UP and DN pump mismatch. Phase
noise in fractional mode is strongly affected by charge pump offset.
DC leakage or “offset” may be added to the UP or DN pumps using cp_UPoffset_sel and cp_DNoffset_sel (Reg08
Table 19). These are 4 bit registers with 28.7uA LSB. Maximum offset is 430uA.
As an example, if the main pump gain was set at 1mA, an offset of 373uA would represent a phase offset of about
(392/1000)*360 = 133degrees.
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