HMC701LP6CE Datasheet, PDF (27/46 Pages) Hittite Microwave Corporation – 8 GHz 16-Bit Fractional-N Synthesizer

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HMC701LP6CE
8 GHz 16-Bit Fractional-N Synthesizer
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(EQ 14)
In this example the output frequency of 2,300,000,002.98 Hz is achieved by programming the 16-bit binary value of
46d = 2Eh = 0000 0000 0010 1110 into dsm_intg.
Similarly the 24-bit binary value of the fractional word is written into dsm_frac,
1d = 000 001h = 0000 0000 0000 0000 0000 0001
Example 2: Set the output to 4.600 025 GHz using a 100 MHz reference, R=2.
Find the nearest integer value, N_int, N_int = 92, f_int = 4.600 000 GHz
This leaves the fractional part to be f_frac =25 kHz
(EQ 15)
Since N_frac must be an integer number, the actual fractional frequency will be 25,001.17 Hz, an error of 1.17 Hz.
Here we program the 16-bit N_int = 92d = 5Ch = 0000 0000 0101 1100 and
the 24-bit N_frac = 8389d = 20C5h = 0000 0010 0000 1100 0101
In addition to the above frequency programming words, the fractional mode must be enabled using the frac register.
Other DSM configuration registers should be set to the recommended values. Register setup files are available on
request.
Integer Frequency
The synthesizer is capable of operating in integer mode. In integer mode the digital Δ∑ modulator is normally shut
off and the division ratio of the VCO divider is set at a fixed value. To run in integer mode set dsm_integer_mode
(Reg12h<3> Table 29) and clear dsm_rstb (Reg01h<13> Table 12). Then program the integer portion of the frequency,
N_INT, as explained by (EQ 13), ignoring the fractional part.
Frequency Hopping Trigger
If the synthesizer is in fractional mode, a write to the fractional frequency register, Reg10h Table 27, will initiate the
frequency hop on the falling edge of the 31^st clock edge of the serial port write (see Figure 29).
If the integer frequency register, Reg0Fh Table 26, is written when in fractional mode the information will be buffered
and only executed when the fractional frequency register is written.
If the synthesizer is in integer mode, a write to the integer frequency register, Reg0Fh Table 26, will initiate the
frequency hop on the falling edge of the 31^st clock edge of the serial port write (see Figure 29).
Power On Reset (POR)
Normally all logic cells in the HMC701LP6CE are reset when the device digital power supply, DVDD, is applied. This
is referred to as Power On Reset, or just POR. POR normally takes about 500us after the DVDD supply exceeds 1.5V,
guaranteed to be reset in 1msec. Once the DVDD supply exceeds 1.5V, the POR will not reset the digital again unless
the supply drops below 100mV.
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