HMC701LP6CE Datasheet, PDF (24/46 Pages) Hittite Microwave Corporation – 8 GHz 16-Bit Fractional-N Synthesizer

v03.0709
HMC701LP6CE
8 GHz 16-Bit Fractional-N Synthesizer
The Lock Detect flag ro_lock_detect (Reg1Fh<0> Table 41) is a read only register, readable from the serial port. The
Lock Detect flag is also output to the LD_SDO pin according to lkd_to_sdo_always (Reg1Ah<13>) and lkd_to_sdo_
automux_en (Reg1Ah<12>), both in Table 36. Setting lkd_to_sdo_always will always display the Lock Detect flag
on LD_DSO. Clearing lkd_to_sdo_always and setting lkd_to_sdo_automux_en will display the Lock Detect flag on
LD_SDO except when a serial port read is requested, in which case the pin reverts temporarily to the Serial Data Out
pin, and returns to the lock detect function after the read is completed.
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Figure 21. Normal Lock Detect Window
Lock Detect with Phase Offset
When operating in fractional mode the linearity of the charge pump and phase detector are more critical than in
integer mode. The phase detector linearity is worse when operated with zero phase offset. Hence in fractional mode
it is necessary to offset the phase of the reference and the VCO at the phase detector. In such a case, for example
with an offset delay, as shown in Figure 22, the mean phase of the VCO will always occur after the reference. The
lock detect circuit window can be made more selective with a fixed offset delay by setting win_asym_enable and
win_asym_up_select (Reg1Ah<11> Table 36). Similarly the offset can be in advance of the reference by clearing
win_asym_up_select while leaving win_asym_enable Reg1Ah<10> set both in Table 36.
Figure 22. Delayed Lock Detect Window
Cycle Slip Prevention (CSP)
When changing frequencies the VCO is not yet locked to the reference and the phase difference at the PFD varies
rapidly over a range much greater than ±2π radians. Since the gain of the PFD varies linearly with phase up to ±2π,
the gain of conventional PFDs will cycle from high gain, when the phase difference approaches a multiple of 2π, to
low gain, when the phase difference is slightly larger than a multiple of 0 radians. This phenomena is known as cycle
slipping. Cycle slipping causes the pull-in rate during the locking phase to vary cyclically as shown in the red curve in
Figure 23. Cycle slipping increases the time to lock to a value far greater than that predicted by normal small signal
Laplace analysis.
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