HD66420 Datasheet, PDF (45/52 Pages) Hitachi Semiconductor – (RAM-Provided 160 Channel 4-Level Grey Scale Driver for Dot Matrix Graphics LCD)

HD66420
It must also be greater than the value set in the blink start raster register. If an inappropriate value is set,
operations may not be correct. Data bits 7 is unused; they should be set to 0 when written to.
Data bit
Set value
7
6
5
4
3
2
1
0
D7 D6 D5 D4 D3 D2 D1 D0
Figure 30 Display Memory Access Register (R4)
Data bit
Set value
7
6
5
4
3
2
1
0
ST6 ST5 ST4 ST3 ST2 ST1 ST0
Figure 31 Display Start Raster register (R5)
Data bit
Set value
7
6
5
4
3
2
1
0
BSL6 BSL5 BSL4 BSL3 BSL2 BSL1 BSL0
Figure 32 Blink Start Raster register (R6)
Data bit
Set value
7
6
5
4
3
2
1
0
BEL6 BEL5 BEL4 BEL3 BEL2 BEL1 BEL0
Figure 33 Blink End Raster register (R7)
Blink Registers (R8 to R10): The blink bit registers (figure 34) designate the 8-bit groups to be blinked.
Setting a bit to 1 blinks the corresponding 8-bit group. Any number of groups can be blinked; setting all the
bits to 1 will blink the entire LCD panel. These bits are valid only when the BLK bit of control register 2 is
1. R10’s data bits 7 to 4 are unused; they should be set to 0 when written to.
Partial Display Block Register (R11): The Partial display block register (figure 35) designates the block
of partial display. Data bits 7 and 4 are unused; they should be set to 0 when written to.
Gray Scale Palette Registers (R12 to R15): The gray scale palette registers (figure 36) designate
the grayscale level or colour. Use these registers to enable an optimal grayscale or colour display. If GRAY
bit is 1, these registers are inactive. Data bits 7 to 5 are unused; they should be set to 0 when written to.
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