HD66420 Datasheet, PDF (43/52 Pages) Hitachi Semiconductor – (RAM-Provided 160 Channel 4-Level Grey Scale Driver for Dot Matrix Graphics LCD)

HD66420
Data bit
Set value
7
6
5
4
3
2
1
0
RMW DISP STBY PWR AMP REV HOLT ADC
Figure 26 Control Register 1 (R0)
Control Register 2 (R1): Control register 2 (figure 27) controls general operations of the HD66420. Each
bit has its own function as described below.
BIS1, BIS0 bits
BIS1, 0 = (1, 1): 1/6 LCD drive levels bias ratio
BIS1, 0 = (1, 0): 1/7 LCD drive levels bias ratio
BIS1, 0 = (0, 1): 1/8 LCD drive levels bias ratio
BIS1, 0 = (0, 0): 1/9 LCD drive levels bias ratio
WLS bit
WLS = l: A word length is 6-bits
WLS = 0: A word length is 8-bits
GRAY bit
GRAY = l : 4-levels of gray scale are fixed
GRAY = 0: 4-levels of gray scale are selected from 32-levels
DTY1,DTY0 bits
DTY1, 0 = (1, 1): 1/8 display duty cycle; partial display mode
DTY1, 0 = (1, 0): 1/32 display duty cycle
DTY1, 0 = (0, 1): 1/64 display duty cycle
DTY1, 0 = (0, 0): 1/80 display duty cycle
INC bit
I NC = l: X address is incremented for each access
INC = 0: Y address is incremented for each access
BLK bit
BLK = 1: Blink function is used
BLK = 0: Blink function is not used
The blink counter is reset when the BLK bit is set to 0. It starts counting and at the same time initiates
blinking when the BLK bit is set to l.
X Address Register (R2): The X address register (figure 28) designates the X address of the display RAM
to be accessed by the MPU. The set value must range from H’00 to H’27 in the case of 8-bit a word or
range from H’00 to H’35 in the case of 6-bit a word; setting a greater value is ignored. The set address is
automatically incremented each time the display RAM is accessed; it is not necessary to update the address
each time. Data bits 7 and 6 are unused; they should be set to 0 when written to.
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