HD66420 Datasheet, PDF (20/52 Pages) Hitachi Semiconductor – (RAM-Provided 160 Channel 4-Level Grey Scale Driver for Dot Matrix Graphics LCD)

HD66420
Configuration of Display Data Bit
Packed Pixel Method
For grey scale display and super reflective colour display, multiple bits are needed for one pixel. In the
HD66420, two bits are assigned to one pixel, enabling a four-level grey scale display and four colour
display.
One address, eight bits, specifies four pixels, and pixel bits 0 and 1 for gray scale are managed as
consecutive bits in one byte.
When grey scale display data is manipulated in bit units, one memory access is sufficient, which enables
smooth high-speed data rewriting.
The bit data to input to pin DB7, DB5, DB3 and DB1 become MSB and the bit data to input via pin DB6,
DB4, DB2 and DB0 are LSB.
LCD display state
Grey scale/colour palette
FRC control circuit
00011011
Bit 7 6 5 4 3 2 1 0
4 pixels/address
Address: n
00001010
76543210
Address: n + 1
Physical memory
Figure 11 Packed Pixel Method
20