HD66420 Datasheet, PDF (41/52 Pages) Hitachi Semiconductor – (RAM-Provided 160 Channel 4-Level Grey Scale Driver for Dot Matrix Graphics LCD)

HD66420
Reset
The low RES signal initializes the HD66420, clearing all the bits in the internal registers. During reset. the
internal registers cannot be accessed.
Note that if the reset conditions specified in the Electric Characteristics section are not satisfied, the
HD66420 will not be correctly initialized. In this case, the internal registers of the HD66420 must be
initialized by software.
Initial Setting of Internal Registers: All the internal register bits are cleared to 0. Details are listed below.
 Normal operation
 Oscillator is active; OSC-OSC1 is used
 Display is off
 Y address of display RAM is incremented
 1/80 duty cycle
 X and Y addresses are 0
 Data in address H’0 is output from the SEGl pin
 Blink function is inactive
 Operational amplifier is disabled
Initial Setting of Pins:
Bus interface pins
During reset, the bus interface pins do not accept signals to access internal registers; data is undefined when
read.
LCD driver output pins
During reset. all the LCD driver output pins (SEG1 to SEGl61, COM1 to COM80) output Vcc-level
voltage, regardless of data value in the display RAM, turning off the LCD. Here, the output voltage is not
alternated. Note that the same voltage (VLCD) is applied to both column and row output pins to prevent
liquid crystals from degrading.
Internal Registers
The HD66420 has one index register and 17 data registers, all of which can be accessed asynchronously
with the internal clock. All the registers except the display memory access register are write-only.
Accessing unused bits or addresses affects nothing; unused bits should be set to 0 when written to.
Index Register (IR): The index register (figure 25) selects one of 17 data registers. The index register
itself is selected when both the CS and RS signals are low. Data bits 7 to 5 are unused; they should be set to
0 when written to.
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