HD66420 Datasheet, PDF (30/52 Pages) Hitachi Semiconductor – (RAM-Provided 160 Channel 4-Level Grey Scale Driver for Dot Matrix Graphics LCD)

HD66420
Partial Display Function
The HD66420 can display only a part of a full display. The bias ratio of this partial display is 1/4 from V_CC
to GND, the duty ratio is 1/8 and rest of display is scanned with unselected levels. 8 levels of contrast can
be selected wit data bit 2 to 0 of R16. The position of this partial display can be located at any position with
using partial display position register. To launch this mode, following processes are needed:
(1) supplied voltage to VLCD must be cut off, PWR bit can be used if external voltage supplier is
controlled with DCON output (R0)
(2) set DTY0, 1 bits (R1)
(3) set COM scanning direction (ADC bit)
(4) set display position (R11, R5)
(5) set contrast level (R16 data-bit 2 to 0)
The clock frequency may be 180kHz at normal display mode. When a partial display is driven, oscillation
frequency will be 18kHz, 1/10 of that of normal display mode. This function is useful for lower power
dissipation. To change clock frequency, follow the process which is showed in Figure 21.
Warning: VLCD must be cut off when partial display mode is launched. Vcc is supplied to LCD
driving circuit instead of VLCD. So if VLCD is supplied externally during partial display mode, Vcc
short-circuit to VLCD.
Table 6 Partial Display Block
R11
H’00
H’01
H’02
H’03
H’04
H’05
H’06
H’07
H’08
H’09
ADC = 1
COM1 → COM8
COM9 → COM16
COM17 → COM24
COM25 → COM32
COM33 → COM40
COM80 → COM73
COM72 → COM65
COM64 → COM57
COM56 → COM49
COM48 → COM41
ADC = 0
COM8 → COM1
COM16 → COM9
COM24 → COM17
COM32 → COM25
COM40 → COM33
COM73 → COM80
COM65 → COM72
COM57 → COM64
COM49 → COM56
COM41 → COM48
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