HD66420 Datasheet, PDF (16/52 Pages) Hitachi Semiconductor – (RAM-Provided 160 Channel 4-Level Grey Scale Driver for Dot Matrix Graphics LCD)

HD66420
Display RAM Configuration and Display
The HD66420 incorporates a bit-mapped display RAM. It has 320 bits in the X direction and 80 bits in the
Y direction. The 320 bits are divided into forty 8-bit groups. As shown in figure 6, data written by the MPU
is stored horizontally with the MSB at the far left and the LSB at the far right. The consecutive two bits
control one pixel of LCD, this means that one 8-bits data contains data which controls four pixels.
The ADC bit of control register 1 can control the positional relationship between X addresses of the RAM
and LCD driver output (figure 7). Specifically. the data in address H’0 is output from SEG1 when the ADC
bit in control register 1 is 0, and from SEG160 otherwise. Here, data in each 8-bit group is also inverted.
Because of this function, the data in X address H’0 can be always displayed on the top left of an LCD panel
with the MSB at the far left regardless of the LSI is positioned with respect to the panel. In this case, DB7,
DB5, DB3 and DB1 are more significant bit in consecutive two bits.
LCD panel
LCD panel
SEG1 SEG3
SEG2 SEG4
Y0 1 1 1 0 0 1 0 0
Y1 ^{0 0 0 1 1 0 1 1}
DDD DDD DD
BBB BBB BB
765 432 10
SEG160
Display RAM
SEG1
Display RAM
SEG157 DEG159
SEG158 SEG160
1 1 1 0 0 1 0 0 Y0
0 0 0 1 1 0 1 1 _Y1
D DD D D D D D
B BB B B B B B
1 03 2 5 4 7 6
(a) ADC = 0
(b) ADC = 1
Figure 7 Display RAM Data and Display
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