HD66420 Datasheet, PDF (23/52 Pages) Hitachi Semiconductor – (RAM-Provided 160 Channel 4-Level Grey Scale Driver for Dot Matrix Graphics LCD)

Table 5 Grayscale Levels (GRAY= 1)
DB7, 5, 3, 1
0
1
DB6, 4, 2, 0
0
1
0
1
HD66420
Grayscale Level
0
1/3
2/3
1
Access to Internal Registers and Display RAM
Access to Internal Registers by the MPU: The internal registers include the index register and data
registers. The index register can be accessed by driving both the CS and RS signals low. To access a data
register, first write its register number ID to the index register with RS set to 0, and then access the data
register with RS set to 1 . Once written, the register number is held until it is rewritten, enabling the same
register to be consecutively accessed without having to rewrite to the register number for each access.
Some data registers contain unused bits; they should be set to 0. Note that all data registers except the
display memory access register can only be written to.
Access to Display RAM by the MPU: To access the display RAM, first write the RAM address desired to
the X address register (R2) and the Y address register (R3). Then read/write the display memory access
register (R4). Memory access by the MPU is independent of memory read by the HD66420 and is also
asynchronous with the HD66420’s clock, thus enabling an interface independent of HD66420’s internal
operations.
However, when reading. data is temporarily latched into a H66420’s buffer and then output next time, a
read is performed in a subsequent cycle. This means that a dummy read is necessary after setting X and Y
addresses. The memory read sequence is shown in figure 12.
X and Y addresses are automatically incremented after each memory access according to the INC bit value
in control register 2; therefore, it is not necessary to update the addresses for each access. Figure 13 shows
two cases of incrementing display RAM address. When the INC bit is 0, the Y address will be incremented
up to H’7F with the X address unchanged. However, actual memory is valid only within H’00_ to H’4F;
accessing an invalid address is ignored. When the INC bit is 1 , the X address will be incremented up to
H’27 or H’35 according to WLS bit with the Y address unchanged. After address H’27 or H’35, the X
address will be returned to H’00; accessing more than forty bytes causes rewriting to the same address.
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