HD66421 Datasheet, PDF (38/46 Pages) Hitachi Semiconductor – (RAM-Provided 160 Channel 4-Level Grey Scale Driver for Dot Matrix Graphics LCD)

Preliminary
Rev. 1.1E '99.02.10
HD66421
Display Memory Access Register (R4): The
display memory access register (figure 37) is used
to access the display RAM. If this register is
write-accessed, data is directly written to the
display RAM. If this register is read-accessed, data
is first latched to this register from the display
RAM and sent out to the data bus on the next read;
therefore, a dummy read access is necessary after
setting the display RAM address.
Display Start Raster Register (R5): The display
start raster register (figure 38) designates the raster
to be displayed at the top of the LCD panel.
Varying the set value scrolls the display vertically.
The set value must be one less than the actual top
raster and less than the duty ratio. If the value is set
outside these ranges, data may not be displayed
correctly. Data bits 7 is unused; they should be set
to 0 when written to.
Blink Start Raster Register (R6): The blink start
raster register (figure 39) designates the top raster
in the area to be blinked. The set value must be
one less than the actual top raster and less than the
duty ratio. If the value is set outside these ranges,
operations may not be correct. Data bits 7 is
unused; they should be set to 0 when written to.
Blink End Raster Register (R7): The blink end
register (figure 40) designates the bottom raster in
the area to be blinked. The area to be blinked is
designated by the blink registers, blink start raster
register, and blink end raster register. The set
value must be one less than the actual bottom
raster and less than the duty ratio. It must also be
greater than the value set in the blink start raster
register. If an inappropriate value is set, operations
may not be correct. Data bits 7 is unused; they
should be set to 0 when written to.
Data bit
Set value
7
6
5
4
3
2
1
0
D7 D6 D5 D4 D3 D2 D1 D0
Figure 37 Display Memory Access Register (R4)
Data bit
Set value
7
6
5
4
3
2
1
0
ST6 ST5 ST4 ST3 ST2 ST1 ST0
Figure 38 Display Start Raster register (R5)
Data bit
Set value
7
6
5
4
3
2
1
0
BSL6 BSL5 BSL4 BSL3 BSL2 BSL1 BSL0
Figure 39 Blink Start Raster register (R6)
Data bit
Set value
7
6
5
4
3
2
1
0
BEL6 BEL5 BEL4 BEL3 BEL2 BEL1 BEL0
Figure 40 Blink End Raster register (R7)
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