HD66421 Datasheet, PDF (28/46 Pages) Hitachi Semiconductor – (RAM-Provided 160 Channel 4-Level Grey Scale Driver for Dot Matrix Graphics LCD)

Preliminary
Rev. 1.1E '99.02.10
HD66421
Partial Display Function
The HD66421 can display only a part of a full
display. The duty ratio of this partial display is 1/8
and rest of display is scanned with unselected
levels. The position of this partial display can be
located at any position with using partial display
position register. To launch this mode, following
processes are needed:
(1) supplied voltage to VLCD must be cut off,
PWR bit can be used if external voltage supplier is
controlled with DCON output (R0)
(2) set DTY bits (R1)
(3) set display position (R11)
(4) set contrast level (R16)
The clock frequency may be 220kHz at normal
display mode. When a partial display is driven,
oscillation frequency will be 18kHz, 1/12.5 of that
of normal display mode. This function is useful for
lower power dissipation. To change clock
frequency, follow the process which is showed in
Figure 28.
Warning:
VLCD must be cut off when partial display
mode is launched. Vcc is supplied to LCD
driving circuit instead of VLCD. So if VLCD
is supplied externally during partial display
mode, Vcc short-circuit to VLCD.
R11
H'00
H'01
H'02
H'03
H'04
H'05
H'06
H'07
H'08
H'09
H'0A
H'0B
Table 6 Partial Display Block
ADC= 0
COM1 –> COM8
COM9 –> COM16
COM17 –> COM24
COM25 –> COM32
COM33 –> COM40
COM41 –> COM48
COM100–> COM93
COM92 –> COM85
COM84 –> COM77
COM76 –> COM69
COM68 –> COM61
COM60 –> COM53
ADC= 1
COM8 –> COM1
COM16 –> COM9
COM24 –> COM17
COM32 –> COM25
COM40 –> COM33
COM48 –> COM41
COM93 –> COM100
COM85 –> COM92
COM77 –> COM84
COM69 –> COM76
COM61 –> COM68
COM53 –> COM60
Y address
H'00
Display
RAM
Start line _R5
R5+7 ^ABCD
LCD Panel
ABCD
R11=H'04
COM1
COM33
COM40
COM49,COM50 (Not used)
COM100
H'63
COM51,COM52 (Not used)
Figure 24 Partial Display
28