HD66421 Datasheet, PDF (16/46 Pages) Hitachi Semiconductor – (RAM-Provided 160 Channel 4-Level Grey Scale Driver for Dot Matrix Graphics LCD)

Preliminary
Rev. 1.1E '99.02.10
HD66421
Display RAM Configuration and Display
The HD66421 incorporates a bit-mapped display
RAM. It has 320 bits in the X direction and 100
bits in the Y direction. The 320 bits are divided
into forty 8-bit groups. As shown in figure 7, data
written by the MPU is stored horizontally with the
MSB at the far left and the LSB at the far right.
The consecutive two bits control one pixel of LCD
in 4-level gray scale mode, this means that one
8-bits data contains data which controls four
pixels. One bit of memory designates one dot of
display in the monochrome display mode.
The ADC bit of control register 1 can control the
positional relationship between X addresses of the
RAM and LCD driver output (figure 8).
Specifically. the data in address H'0 is output
from SEG1 when the ADC bit in control register
1 is 0, and from SEG160 otherwise. Here. data in
each 8-bit group is also inverted. Because of this
function, the data in X address H'0 can be always
displayed on the top left of an LCD panel with the
MSB at the far left regardless of the LSI is
positioned with respect to the panel. In this case,
DB7, DB5, DB3 and DB1 are more significant bit
in consecutive two bits.
LCD panel
LCD panel
SEG1 SEG3
SEG2 SEG4
Y0 _{1 1 1 0 0 1 0 0}
Y1 0 0 0 1 1 0 1 1
DDDDDD DD
BBBBBB BB
765432 10
SEG160
Display RAM
SEG1
Display RAM
SEG157 DEG159
SEG158 SEG160
1 1 1 0 0 1 0 0 ^Y0
0 0 0 1 1 0 1 1 Y1
D DDDDDDD
B BBBBBBB
1 0325476
(a) MON = 0, ADC = 0, WLS= 0
(b) MON = 0, ADC = 1 , WLS= 0
Figure 7 Display RAM Data and Display in Gray Scale Mode
SEG1
H'00
H'01
LCD drive signal output
SEG160 SEG1
H'00
H'01
LCD drive signal output
SEG160
H'62
H'63
H'0
MSB
H'1 _{X addresses}
H'62
H'63
H'27
(a) MON = 0, ADC = 0, WLS= 0
H'27 H'26
X addresses
H'0
MSB
(b) MON = 0, ADC = 1, WLS= 0
Figure 8 Display RAM Configuration in Gray Scale Mode
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