HD66421 Datasheet, PDF (25/46 Pages) Hitachi Semiconductor – (RAM-Provided 160 Channel 4-Level Grey Scale Driver for Dot Matrix Graphics LCD)

Preliminary
Rev. 1.1E '99.02.10
HD66421
Arbitration Control
The HD66421 controls the arbitration between
draw access and display access. The draw access
read and write display data of display
memory incorporated in the HD66421. The
display access outputs display data to the liquid
crystal panel. The draw access has the priority
over display access, so continuous access is
enabled without having the system to wait. For
arbitration control, draw access is recognized as
valid when CS and WR/RD are low.
When draw and display access occur at the same
time, draw access is executed prior to display
access. Display access is executed between two
draw access during display access period. If a
period of one draw access is longer than that of
display access, display access will not be
executed properly. If this condition happens
frequently, flicker will be seen on the display.
The low level width of WR and RD must be less
than the period of display access - 450ns.
CS
WR
RD
Draw access
Display access
period
Draw access
Figure 19 Definition of Draw Access
Display Access Period
WR
period of 4 clocks (22µs approx ) *
CS
Memory Access
* In the case of fOSC = 180kHz
Draw Access
Display Access
Figure 20 Memory Access when Display and Draw Access Occur at The Same Time
Display Access Period
WR
period of 4 clocks (22us approx. ) *
period of 4 clocks - 450ns
CS
Memory Access
Draw Access
* In the case of fOSC = 180kHz
Figure 21 WR Low Level Width
Display Access
(min. 450ns)
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