HD66421 Datasheet, PDF (23/46 Pages) Hitachi Semiconductor – (RAM-Provided 160 Channel 4-Level Grey Scale Driver for Dot Matrix Graphics LCD)

Preliminary
Rev. 1.1E '99.02.10
HD66421
Display RAM Reading by LCD Controller:
Data is read by the HD66421 to be displayed
asynchronously with accesses by the MPU.
However, because simultaneous access could
damaging data in the display RAM, the HD66421
internally arbitrates access timing; access by the
MPU usually has priority and so access by the
HD66421 is placed between accesses by the MPU.
Accordingly, an appropriate time must be secured
(see the given electrical characteristics between
two accesses by the MPU).
H'0
H'00
H'01
H'63
H'1
Valid area
H'27 H'28
H'35
Valid area (WLS= 1)
H'7F
H'0
H'00
H'01
H'02
Invalid area
Invalid area
WLS= 0
(a) INC = 0
WLS= 1
H'1
WLS= 0
H'27
H'28
WLS= 1
H'35
H'63
WLS= 0
WLS= 1
(b) INC = 1, MON= 0
H'0
H'2
H'00
H'01
WLS= 0
H'02
H'26
H'28
WLS= 1
H'34
H'63
WLS= 0
WLS= 1
(c) INC = 1, MON= 1
Figure 17 Display Address Increment
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