HD66421 Datasheet, PDF (35/46 Pages) Hitachi Semiconductor – (RAM-Provided 160 Channel 4-Level Grey Scale Driver for Dot Matrix Graphics LCD)

Preliminary
Rev. 1.1E '99.02.10
HD66421
Reset
The low RES signal initializes the HD66421,
clearing all the bits in the internal registers. During
reset. the internal registers cannot be accessed.
Initial Setting of Pins:
Bus interface pins
During reset, the bus interface pins do not accept
signals to access internal registers; data is
undefined when read.
Note that if the reset conditions specified in the
Electric Characteristics section are not satisfied,
the HD66421 will not be correctly initialized. In
this case, the internal registers of the HD66421
must be initialized by software.
Initial Setting of Internal Registers: All the
internal register bits are cleared to 0. Details are
listed below.
LCD driver output pins
During reset. all the LCD driver output pins
(SEG1 to SEGl61, COM1 to COM100) output
Vcc-level voltage, regardless of data value in the
display RAM, turning off the LCD. Here, the
output voltage is not alternated. Note that the
same voltage (VLCD) is applied to both column
and row output pins to prevent liquid crystals
from degrading.
- Normal operation
- Oscillator is active; OSC-OSC1 is used
- Display is off
- Y address of display RAM is incremented
- 1/100 duty cycle
- X and Y addresses are 0
- Data in address H'0 is output from the SEGl pin
- Blink function is inactive
- Operational amplifier is disabled
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