HD66421 Datasheet, PDF (37/46 Pages) Hitachi Semiconductor – (RAM-Provided 160 Channel 4-Level Grey Scale Driver for Dot Matrix Graphics LCD)

Preliminary
Rev. 1.1E '99.02.10
HD66421
Control Register 2 (R1): Control register 2 The blink counter is reset when the BLK bit is set
(figure 34) controls general operations of the to 0. It starts counting and at the same time
HD66421. Each bit has its own function as initiates blinking when the BLK bit is set to l.
described below.
X Address Register (R2): The X address register
BIS1, BIS0 bits
(figure 35) designates the X address of the
BIS1, 0 = (1, 1): 1/8 LCD drive levels bias ratio display RAM to be accessed by the MPU. The set
BIS1, 0 = (1, 0): 1/9 LCD drive levels bias ratio value must range from H'00 to H'27 in the case of
BIS1, 0 = (0, 1): 1/10 LCD drive levels bias ratio 8-bit a word or range from H'00 to H'35 in the
BIS1, 0 = (0, 0): 1/11 LCD drive levels bias ratio case of 6-bit a word; setting a greater value is
ignored. The set address is automatically
WLS bit
incremented each time the display RAM is
WLS = l: A word length is 6-bits
accessed; it is not necessary to update the address
WLS = 0: A word length is 8-bits
each time. Data bits 7 and 6 are unused; they
should be set to 0 when written to. When you use
GRAY bit
monochrome display, the set value must range the
GRAY = l : 4-levels of gray scale are fixed
even number from H'00 to H'26 in the case of
GRAY = 0: 4-levels of gray scale are selected
8-bit a word or range from H'00 to H'34 in the
from 32-levels
case of 6-bit a word.
DTY1,DTY0 bits
Y Address Register (R3): The Y address register
DTY1, 0 = (1, 1): 1/8 display duty cycle; partial (figure 36) designates the Y address of the
display mode
display RAM to be accessed by the MPU. The set
DTY1, 0 = (1, 0): 1/64 display duty cycle
value must range from H'00 to H'40; setting a
DTY1, 0 = (0, 1): 1/80 display duty cycle
greater value is ignored. The set address is
DTY1, 0 = (0, 0): 1/100 display duty cycle
automatically incremented each time the display
RAM is accessed; it is not necessary to update the
INC bit
address each time. Data bit 7 is unused; it should
I NC = l: X address is incremented for each access be set to 0 when written to.
INC = 0: Y address is incremented for each access
BLK bit
BLK = 1: Blink function is used
BLK = 0: Blink function is not used
Data bit
Set value
7
6
5
4
3
2
1
0
BIS1 BIS0 WLS GRAY DTY1 DTY0 INC BLK
Figure 34 Control Register 2 (R1)
Data bit
Set value
7
6
5
4
3
2
1
0
XA5 XA4 XA3 XA2 XA1 XA0
Figure 35 X address Register (R2)
Data bit
Set value
765 43210
YA6 YA5 YA4 YA3 YA2 YA1 YA0
Figure 36 Y address Register (R3)
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