GS832418B Datasheet, PDF (6/46 Pages) GSI Technology – 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs

Preliminary
GS832418(B/C)/GS832436(B/C)/GS832472(C)
GS832418/36/72 209-Bump BGA Pin Description
Pin Location
D6
A7
A5, A6
P6
L6
T6
N6
G6
A4
H6, J6, K6, M6
A8, N6
B6
Symbol
G
ADV
ADSP, ADSC
ZZ
FT
LBO
SCD
MCH
MCH
MCL
MCL
BW
F6
ZQ
W3
W4
W8
W9
E5, E6, E7, G5, G7, J5, J7, L5, L7, N5, N7, R5,
R6, R7
D3, D9, F3, F4, F5, F7, F8, F9, H3, H4, H5, H7,
H8, H9, K5, K7, M3, M4, M5, M7, M8, M9, P3,
P4, P5, P7, P8, P9, T3, T9
E3, E4, E8, E9, G3, G4, G8, G9, J3, J4, J8, J9,
L3, L4, L8, L9, N3, N4, N8, N9, R3, R4, R8, R9
TMS
TDI
TDO
TCK
V_DD
V_SS
V_DDQ
Type
I
I
I
I
I
I
I
I
I
I
I
I
I
O
I
I
I
I
Description
Output Enable; active low
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Single Cycle Deselect/Dual Cycle Deselect Mode Control (
x72/x36 Versions)
Must Connect High
Must Connect High (x18 version)
Must Connect Low
Must Connect Low (x18 version)
Byte Enable; active low
FLXDrive Output Impedance Control
(Low = Low Impedance [High Drive], High = High Impedance [Low
Drive])
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
Core power supply
I/O and Core Ground
Output driver power supply
Rev: 1.00 10/2001
6/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.