GS832418B Datasheet, PDF (1/46 Pages) GSI Technology – 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs

Preliminary
GS832418(B/C)/GS832436(B/C)/GS832472(C)
119- and 209-Pin BGA _{2M x 18, 1M x 36, 512K x 72}
250 MHz–133MHz
Commercial Temp
Industrial Temp
36Mb S/DCD Sync Burst SRAMs
2.5 V or 3.3 V V_DD
2.5 V or 3.3 V I/O
Features
• FT pin for user-configurable flow through or pipeline operation
• Single/Dual Cycle Deselect selectable (x36 and x72)
• Dual Cycle Deselect only (x18)
• IEEE 1149.1 JTAG-compatible Boundary Scan
• ZQ mode pin for user-selectable high/low output drive
• 2.5 V or 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to SCD x36/x72 Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 119- and 209-bump BGA package
-250 -225 -200 -166 -150 -133 Unit
Pipeline
3-1-1-1
t_KQ
tCycle
2.3 2.5 3.0 3.5 3.8 4.0 ns
4.0 4.4 5.0 6.0 6.6 7.5 ns
Curr (x18) 365 335 305 265 245 215 mA
3.3 V Curr (x36) 560 510 460 400 370 330 mA
Curr (x72) 660 600 540 460 430 380 mA
Curr (x18) 360 330 305 260 240 215 mA
2.5 V Curr (x36) 550 500 460 390 360 330 mA
Curr (x72) 640 590 530 450 420 370 mA
Flow
Through
2-1-1-1
t_KQ
tCycle
6.0 6.5 7.5 8.5 10 11 ns
7.0 7.5 8.5 10 10 15 ns
Curr (x18) 235 230 210 200 195 150 mA
3.3 V Curr (x36) 300 300 270 270 270 200 mA
Curr (x72) 350 350 300 300 300 220 mA
Curr (x18) 235 230 210 200 195 145 mA
2.5 V Curr (x36) 300 300 270 270 270 190 mA
Curr (x72) 340 340 300 300 300 220 mA
Functional Description
Applications
The GS832418/36/72 is a 37,748,736-bit high performance 2-die
synchronous SRAM module with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device now
finds application in synchronous SRAM applications, ranging
from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the
user via the FT mode . Holding the FT mode pin low places the
RAM in Flow Through mode, causing output data to bypass the
Data Output Register. Holding FT high places the RAM in
Pipeline mode, activating the rising-edge-triggered Data Output
Register.
SCD and DCD Pipelined Reads
The GS832436(B/C) and the GS832472(C) are SCD (Single
Cycle Deselect) and DCD (Dual Cycle Deselect) pipelined
synchronous SRAMs. The GS832418(B/C) is a DCD-only
SRAM. DCD SRAMs pipeline disable commands to the same
degree as read commands. SCD SRAMs pipeline deselect
commands one stage less than read commands. SCD RAMs begin
turning off their outputs immediately after the deselect command
has been captured in the input registers. DCD RAMs hold the
deselect command for one full cycle and then begin turning off
their outputs just after the second rising edge of clock. The user
may configure the x36 or x72 versions of this SRAM for either
mode of operation using the SCD mode input.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.
FLXDrive™
The ZQ pin allows selection between high drive strength (ZQ low)
for multi-drop bus applications and normal drive strength (ZQ
floating or high) point-to-point applications. See the Output Driver
Characteristics chart for details.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High)
of the ZZ signal, or by stopping the clock (CK). Memory data is
retained during Sleep mode.
Core and Interface Voltages
The GS832418/36/72 operates on a 2.5 V or 3.3 V power supply.
All input are 3.3 V and 2.5 V compatible. Separate output power
(V_DDQ) pins are used to decouple output noise from the internal
circuits and are 3.3 V and 2.5 V compatible.
Rev: 1.00 10/2001
1/46
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology).
© 2001, Giga Semiconductor, Inc.