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GS832418B Datasheet, PDF (20/46 Pages) GSI Technology – 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs | |||
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Preliminary
GS832418(B/C)/GS832436(B/C)/GS832472(C)
Power Supply Voltage Ranges
Parameter
Symbol Min.
Typ.
Max.
Unit Notes
3.3 V Supply Voltage
VDD3
3.0
3.3
3.6
V
2.5 V Supply Voltage
VDD2
2.3
2.5
2.7
V
3.3 V VDDQ I/O Supply Voltage
VDDQ3
3.0
3.3
3.6
V
2.5 V VDDQ I/O Supply Voltage
VDDQ2
2.4
2.5
2.7
V
Notes:
1. The part numbers of Industrial Temperature Range versions end the character âIâ. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be â2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
VDDQ3 Range Logic Levels
Parameter
Symbol Min.
Typ.
Max.
Unit Notes
VDD Input High Voltage
VDD Input Low Voltage
VDDQ I/O Input High Voltage
VIH
1.7
â
VDD + 0.3
V
1
VIL
â0.3
â
0.8
V
1
VIHQ
1.7
â
VDDQ + 0.3
V
1,3
VDDQ I/O Input Low Voltage
VILQ
â0.3
â
0.8
V
1,3
Notes:
1. The part numbers of Industrial Temperature Range versions end the character âIâ. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be â2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
VDDQ2 Range Logic Levels
Parameter
Symbol Min.
Typ.
Max.
Unit Notes
VDD Input High Voltage
VIH
0.6*VDD
â
VDD + 0.3
V
1
VDD Input Low Voltage
VIL
â0.3
â
0.3*VDD
V
1
VDDQ I/O Input High Voltage
VIHQ
0.6*VDD
â
VDDQ + 0.3
V
1,3
VDDQ I/O Input Low Voltage
VILQ
â0.3
â
0.3*VDD
V
1,3
Notes:
1. The part numbers of Industrial Temperature Range versions end the character âIâ. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be â2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
Rev: 1.00 10/2001
20/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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