GS832418B Datasheet, PDF (13/46 Pages) GSI Technology – 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs

Preliminary
GS832418(B/C)/GS832436(B/C)/GS832472(C)
Mode Pin Functions
Mode Name
Pin
Name
State
Function
Burst Order Control
LBO
L
H
Linear Burst
Interleaved Burst
Output Register Control
FT
L
H or NC
Flow Through
Pipeline
Power Down Control
Single/Dual Cycle Deselect Control
L or NC
ZZ
H
SCD
L
H or NC
Active
Standby, I_DD = I_SB
Dual Cycle Deselect
Single Cycle Deselect
FLXDrive Output Impedance Control
ZQ
L
H or NC
High Drive (Low Impedance)
Low Drive (High Impedance)
Note:
There are pull-up devices on the ZQ, SCD and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the
chip will operate in the default states as specified in the above tables.
Enable / Disable Parity I/O Pins
This SRAM allows the user to configure the device to operate in Parity I/O active (x18, x36, or x72) or in Parity I/O inactive (x16,
x32, or x64) mode. Holding the PE bump low or letting it float will activate the 9th I/O on each byte of the RAM. Grounding PE
deactivates the 9th I/O of each byte, although the bit in each byte of the memory array remains active to store and recall parity bits
generated and read into the ByteSafe parity circuits.
Burst Counter Sequences
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
Note: The burst counter wraps to initial state on the 5th clock.
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 1.00 10/2001
13/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.