GS832418B Datasheet, PDF (28/46 Pages) GSI Technology – 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs

Pipelined SCD Read Cycle Timing
Preliminary
GS832418(B/C)/GS832436(B/C)/GS832472(C)
CK
ADSP
ADSC
ADV
A0–An
GW
BW
Single Read
tS ^tH
Burst Read
tKH ^tKL
tKC
ADSP is blocked by E inactive
tS tH
ADSC initiated read
tS tH
Suspend Burst
tS tH
RD1
tS
RD2
RD3
tH
tS
tH
BWA–BWD
E1
tS tH
E1 masks ADSP
tOE
G
tOHZ
tOLZ
tKQX
DQA–DQD
Hi-Z
Q1A
Q2A Q2B
Q2c
tLZ
tKQ
tKQX
Q2D
Q3A
tHZ
Rev: 1.00 10/2001
28/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.