GS832418B Datasheet, PDF (30/46 Pages) GSI Technology – 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs

Preliminary
GS832418(B/C)/GS832436(B/C)/GS832472(C)
Pipelined DCD Read Cycle Timing
CK
ADSP
ADSC
ADV
A0–An
GW
BW
Single Read
tS tH
Burst Read
tKL
tKH
tKC ^{ADSP is blocked by E1 inactive}
tS tH _{ADSC initiated read}
tS tH
Suspend Burst
tS _tH
RD1
tS
RD2
RD3
tH
tS
tH
BA–BD
E1
G
DQA–DQD
tS tH
tOE
tOLZ
Hi-Z
tLZ
tOHZ
Q1A
tKQ
E1 masks ADSP
tKQX
Q2A Q2B
Q2c
Q2D
tKQX
Q3A
tHZ
Rev: 1.00 10/2001
30/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.