GS4576C09 Datasheet, PDF (48/62 Pages) GSI Technology – 64M x 9, 32M x 18, 16M x 36 576Mb CIO Low Latency DRAM (LLDRAM II)

GS4576C09/18/36L
AC Electrical Characteristics (Continued)
Parameter
Symbol
–18
Min
Max
–24
Min
Max
–25
Min
Max
–33
Min
Max
Refresh
Average Periodic Refresh
Interval
tREFI
—
0.24
—
0.24
—
0.24
—
0.24
 10
Notes:
1. All timing parameters are measured relative to the crossing point of CK/CK, DK/DK and to the crossing point with V_REF of the command,
address, and data signals.
2. Outputs measured with equivalent load:
V_TT
50 
DQ
Test Point
10 pF
V_OUT
3. Tests for AC timing I_DD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the
related specifications and device operations are tested for the full voltage range specified.
4. AC timing may use a V_IL– to–V_IH swing of up to 1.5 V in the test environment, but input timing is still referenced to V_REF (or to the crossing
point for CK/CK), and parameter specifications are tested for the specified AC input levels under normal use conditions. The minimum slew
rate for the input signals used to test the device is 2 V/ns in the rance between V_IL(AC) and V_IH(AC).
5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
6. Frequency drift is not allowed.
7. tQKQ0 is referenced to DQ0–DQ17 for the x36 xconfiguration and DQ0–DQ8 for the x18 configuration. tQKQ1 is referenced to
DQ18–DQ35 for the x36 configuration and the DQ9–DQ17 for the x18 configuration.
8. tQKQ takes in to account the skew between any QKx and any Q.
9. tDVW (MIN) tQHP – (tQKQx [MAX] + |tQKQx [MIN]|)
10. To improve efficiency, eight AREF commands (one for each bank) can be posted to the LLDRAM II on consecutive cycles at periodic
intervals of 1.95 s
Rev: 1.04 11/2013
48/62
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology