GS4576C09 Datasheet, PDF (28/62 Pages) GSI Technology – 64M x 9, 32M x 18, 16M x 36 576Mb CIO Low Latency DRAM (LLDRAM II)

GS4576C09/18/36L
Address Multiplexing
LLDRAM II defaults to “broadside” addressing at power up, meaning, it registers all address inputs on a single clock transition.
However, for most configurations of the device, considerable efficiency can be gained by operating in Address Multiplexed mode,
cutting the address pin count on the host device in half. In Multiplexed Address mode, the address is loaded in two consecutive
clock transitions. Broadside Addressing only improves Continuous Burst mode data transfer efficiency of Burst Length 2 (BL = 2)
configuration.
In Address Multiplex mode, bank addresses are loaded on the same clock transition as Command and the first half of the address,
Ax. The 576Mb Address Mapping in Multiplexed Address Mode table and Cycle Time and Read/Write Latency Configuration in
Mulitplexed Mode table show the addresses needed for both the first and second clock transitions (Ax and Ay, respectively). The
AREF command does not require an address on the second clock transition, as only the Bank Address are loaded for refresh
commands. Therefore, AREF commands may be issued on consecutive clocks, even when in Address Multiplex mode.
Setting Mode Register Bit 5 (M5) to 1 in the Mode Register activates the Multiplexed Address mode. Once this bit is set
subsequent MRS, READ, and WRITE operate as described in the Multiplexed Address Mode diagram.
Rev: 1.04 11/2013
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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