GS4576C09 Datasheet, PDF(39/62 Page) GSI Technology – 64M x 9, 32M x 18, 16M x 36 576Mb CIO Low Latency DRAM (LLDRAM II)

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

GS4576C09 Datasheet, PDF (39/62 Pages) GSI Technology – 64M x 9, 32M x 18, 16M x 36 576Mb CIO Low Latency DRAM (LLDRAM II)

◁

GS4576C09/18/36L

Recommended DC Operating Conditions and Electrical Characteristics

Description

Conditions Symbol

Min.

Max.

Unit Notes

Supply Voltage

VEXT

2.38

2.63

Supply Voltage

VDD

1.7

1.9

Isolated Output Buffer Supply

VDDQ

1.4

VDD

2, 3

Reference Voltage

VREF

0.49 * VDDQ

0.51 * VDDQ

V 4, 5, 6

Termination Voltage

VTT

0.95 * VREF

1.05 * VREF

7, 8

Input High (logic 1) voltage

VIH(DC)

VREF + 0.1

VDDQ + 0.3

Input Low (logic 0) voltage

VIL(DC)

VSS â 0.3

VREF â 0.1

Ouput High Current

VOUT = VDDQ/2

IOH

(VDDQ/2)/(1.15 * RQ/5) (VDDQ/2)/(0.85 * RQ/5) A 9, 10, 11

Ouput Low Current

VOUT = VDDQ/2

IOL

(VDDQ/2)/(1.15 * RQ/5) (VDDQ/2)/(0.85 * RQ/5) A 9, 10, 11

Clock Input Leakage Current 0 Vï£ VIN ï£ï VDD

ILC

â5

ïA

Input Leakage Current

0 Vï£ VIN ï£ï VDD

ILI

â5

ïA

Output Leakage Current

0 Vï£ VIN ï£ï VDDQ

ILO

â5

ïA

Reference Voltage Current

IREF

â5

ïA

Notes:

1. All voltages referenced to VSS (GND). This note applies to the entire table.

2. Overshoot VIH(AC) ï£ VDD+ 0.7 V for t ï£ tCK/2. Undershoot: VIL(AC) ï³ â0.5 V for t ï£ tCK/2. During normal operation VDDQ must not exceed

VDD. Control input signals may not have pulse widthts less than tCK/2 or operate at frequencies exceeding tCK (MAX).

3. VDDQ can be set to a nominal 1.5 V Â± 0.1 V or 1.8 V Â± 0.1 V supply.

4. Typically the value of VREF is expected to be 0.5 * VDDQ of the transmitting device. VREF is expected to track variations in VDDQ.

5. Peak-to-Peak AC noise on VREF must not exceed Â±2% of VREF(DC).

6. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise ï

(non-common mode) on VREF may not exceed Â±2% of the DC value. Thus, from VDDQ/2, VREF is allowed Â±2% VDDQ/2 for DC error and an

addtional Â±2% VDDQ/2 for AC noise. This measurement is to be taken at the nearest VREF bypass capacitor.

7. VTT is expected to be set equal to VREF and must track variations in the DC level of VREF.

8. On-die termination may be selected using Mode Register Bit 9 (M9). A resistance RTT from each data input signal to the nearest VTT can be

enabled. RTT = 125ïâ185ïï at 95Â° C TC.

9. IOH and IOL are defined as absolute values and are measured at VDDQ/2. IOH flows from the device, IOL flows into the device.

10. If Mode Register Bit 8 (M8) is 0, use RQ = 250ïï in the equation in lieu of presence of an external impedance matched resistor.

11. For VOL and VOH, refer to the LLDRAM II IBIS models.

Rev: 1.04 11/2013

39/62

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

▷